Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation

Taehwan Kim; Jongsun Park

doi:10.1109/ISOCC56007.2022.10031535

Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation

Taehwan Kim, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Spin-orbit torque magnetic random access memory (SOT-MRAM) has recently gained great attention due to its various benefits on memory implementation. However, SOT-MRAM's read operation still shows large delay with large energy consumption, making it difficult to replace conventional CMOS-based memories. In this paper, a source-line shared (SLS) 2T SOT-MRAM cell structure is presented, where the bit-line capacitance is effectively reduced to benefit the speed and energy of the read operation. While achieving benefits in read operation, the area overhead of the SLS SOT-MRAM cell can be efficiently reduced by sharing the source line among 4 cells. The HSPICE circuit simulations using the 28 nm CMOS technology show that the proposed SLS 2T SOT-MRAM cell achieves the read energy improvement of 28.5% and read speed improvement of 37.8% while showing only 6.25% of area overhead.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3-4
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031535
Publication status	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 2022 Oct 19 → 2022 Oct 22

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	22/10/19 → 22/10/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

read operation
spin-orbit torque (SOT) mram

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Hardware and Architecture
Safety, Risk, Reliability and Quality

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISOCC56007.2022.10031535

Cite this

Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation. / Kim, Taehwan; Park, Jongsun.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 3-4 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, T & Park, J 2022, Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 3-4, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 22/10/19. https://doi.org/10.1109/ISOCC56007.2022.10031535

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keywords = "read operation, spin-orbit torque (SOT) mram",

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doi = "10.1109/ISOCC56007.2022.10031535",

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series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

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AB - Spin-orbit torque magnetic random access memory (SOT-MRAM) has recently gained great attention due to its various benefits on memory implementation. However, SOT-MRAM's read operation still shows large delay with large energy consumption, making it difficult to replace conventional CMOS-based memories. In this paper, a source-line shared (SLS) 2T SOT-MRAM cell structure is presented, where the bit-line capacitance is effectively reduced to benefit the speed and energy of the read operation. While achieving benefits in read operation, the area overhead of the SLS SOT-MRAM cell can be efficiently reduced by sharing the source line among 4 cells. The HSPICE circuit simulations using the 28 nm CMOS technology show that the proposed SLS 2T SOT-MRAM cell achieves the read energy improvement of 28.5% and read speed improvement of 37.8% while showing only 6.25% of area overhead.

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Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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