Spin-orbit torque magnetic random access memory (SOT-MRAM) has recently gained great attention due to its various benefits on memory implementation. However, SOT-MRAM's read operation still shows large delay with large energy consumption, making it difficult to replace conventional CMOS-based memories. In this paper, a source-line shared (SLS) 2T SOT-MRAM cell structure is presented, where the bit-line capacitance is effectively reduced to benefit the speed and energy of the read operation. While achieving benefits in read operation, the area overhead of the SLS SOT-MRAM cell can be efficiently reduced by sharing the source line among 4 cells. The HSPICE circuit simulations using the 28 nm CMOS technology show that the proposed SLS 2T SOT-MRAM cell achieves the read energy improvement of 28.5% and read speed improvement of 37.8% while showing only 6.25% of area overhead.
|Title of host publication||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of|
Duration: 2022 Oct 19 → 2022 Oct 22
|Name||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Conference||19th International System-on-Chip Design Conference, ISOCC 2022|
|Country/Territory||Korea, Republic of|
|Period||22/10/19 → 22/10/22|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.
© 2022 IEEE.
- read operation
- spin-orbit torque (SOT) mram
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality