Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors

Eun Ae Chung; Young Pil Kim; Min Chul Park; Kab Jin Nam; Sung Sam Lee; Ji Young Min; Giyoung Yang; Yu Gyun Shin; Siyoung Choi; Gyoyoung Jin; Joo Tae Moon; Sangsig Kim

doi:10.1109/LED.2010.2085416

Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors

Eun Ae Chung, Young Pil Kim, Min Chul Park, Kab Jin Nam, Sung Sam Lee, Ji Young Min, Giyoung Yang, Yu Gyun Shin, Siyoung Choi, Gyoyoung Jin, Joo Tae Moon, Sangsig Kim

Research output: Contribution to journal › Article › peer-review

Abstract

The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying FowlerNordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.

Original language	English
Article number	5629430
Pages (from-to)	81-83
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	32
Issue number	1
DOIs	https://doi.org/10.1109/LED.2010.2085416
Publication status	Published - 2011 Jan

Bibliographical note

Funding Information:
Manuscript received September 17, 2010; accepted September 28, 2010. Date of publication November 11, 2010; date of current version December 27, 2010. This paper was supported by the Samsung–Korea University Semiconductor Research Center. The review of this letter was arranged by Editor C. Bulucea.

Keywords

Cell transistor
MOSFET
charge pumping (CP)
interface traps
recessed-channel array transistor (RCAT)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2010.2085416

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title = "Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors",

abstract = "The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying FowlerNordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.",

keywords = "Cell transistor, MOSFET, charge pumping (CP), interface traps, recessed-channel array transistor (RCAT)",

author = "Chung, {Eun Ae} and Kim, {Young Pil} and Park, {Min Chul} and Nam, {Kab Jin} and Lee, {Sung Sam} and Min, {Ji Young} and Giyoung Yang and Shin, {Yu Gyun} and Siyoung Choi and Gyoyoung Jin and Moon, {Joo Tae} and Sangsig Kim",

note = "Funding Information: Manuscript received September 17, 2010; accepted September 28, 2010. Date of publication November 11, 2010; date of current version December 27, 2010. This paper was supported by the Samsung–Korea University Semiconductor Research Center. The review of this letter was arranged by Editor C. Bulucea.",

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doi = "10.1109/LED.2010.2085416",

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AU - Kim, Young Pil

AU - Park, Min Chul

AU - Nam, Kab Jin

AU - Lee, Sung Sam

AU - Min, Ji Young

AU - Yang, Giyoung

AU - Shin, Yu Gyun

AU - Choi, Siyoung

AU - Jin, Gyoyoung

AU - Moon, Joo Tae

AU - Kim, Sangsig

N1 - Funding Information: Manuscript received September 17, 2010; accepted September 28, 2010. Date of publication November 11, 2010; date of current version December 27, 2010. This paper was supported by the Samsung–Korea University Semiconductor Research Center. The review of this letter was arranged by Editor C. Bulucea.

PY - 2011/1

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N2 - The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying FowlerNordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.

AB - The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying FowlerNordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.

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KW - recessed-channel array transistor (RCAT)

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Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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