Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors

The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying FowlerNordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.