Spike Counts based Low Complexity SNN Architecture with Binary Synapse

Keyphrases

• Neural Network Architecture 100%
• Spike Count 100%
• Spiking Neural Networks 100%
• Binary Synapses 100%
• Neural Network Processor 60%
• Operation Mode 40%
• Postsynaptic Density Protein 95 (PSD-95) 40%
• Energy Efficient 40%
• Energy Consumption 20%
• Learning Approaches 20%
• Learning Methods 20%
• Spontaneous Excitatory Postsynaptic Current (sEPSC) 20%
• Synaptic 20%
• Reduction Method 20%
• Design Techniques 20%
• Complexity Reduction 20%
• Learning Process 20%
• Implementation Results 20%
• Axon 20%
• Unsupervised Learning 20%
• Bit-width 20%
• Energy Efficiency Improvement 20%
• 65nm CMOS 20%
• Hardware Efficiency 20%
• 1-bit 20%
• Recognition Accuracy 20%
• Area-efficient 20%
• Weight Update 20%
• MNIST 20%
• Excitatory Neurons 20%
• Learning Styles 20%
• Neural Network Design 20%
• Low-complexity Design 20%
• Computing Schemes 20%
• Count-based Methods 20%
• Number of Spikes 20%

Computer Science

• Neural Network 100%
• Neural Network Architecture 100%
• Network Processor 75%
• Synaptic Weight 50%
• Learning Approach 25%
• Energy Efficiency 25%
• Energy Consumption 25%
• Energy Efficient 25%
• Complexity Reduction 25%
• Learning Process 25%
• Network Design 25%
• Recognition Accuracy 25%
• Design Technique 25%
• Unsupervised Learning 25%
• Computer Hardware 25%