SPTPL: A new pulsed latch type flip-flop in high-performance system-on-a-chip (SoC)

Inhwa Jung, Moo Young Kim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


In many VLSI chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Traditionally, two approaches have been used: (1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; (2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. Recently, pulsed latch type flip-flops are introduced in several high-performance microprocessors to reduce E × D. In this paper, these flip-flops are described with their pros and cons. Then, a new circuit technique is described along with simulation results. The proposed pulsed latch reduces E × D by 82.6% to 95.4% compared to conventional flip-flops.

Original languageEnglish
Pages (from-to)169-179
Number of pages11
JournalJournal of Circuits, Systems and Computers
Issue number2
Publication statusPublished - 2007 Apr

Bibliographical note

Funding Information:
This work is financially supported by the Ministry of Education and Human Resources Development (MOE), the Ministry of Commerce, Industry, and Energy (MOCIE) and the Ministry of Labor (MOLAB) through the fostering project of the Lab of Excellency.


  • Clock tree
  • Flip-flop
  • Low-power
  • Small-swing
  • Statistical power saving

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'SPTPL: A new pulsed latch type flip-flop in high-performance system-on-a-chip (SoC)'. Together they form a unique fingerprint.

Cite this