SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation

Hyeyeong Lee; Joonhyung Kim; Jongsun Park

doi:10.1109/ISOCC56007.2022.10031591

SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation

Hyeyeong Lee, Joonhyung Kim, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Since power consumption reduction has been of particular interest, lowering supply voltage has been widely adopted in system on a chip (SoC) design. In static random access memory (SRAM), read operation with low supply voltage suffers from large read delay to develop the bit-line (BL) voltages using reduced bitcell current. In addition, since process-voltage - temperature (PVT) variations in bitcell current deteriorates at low supply voltage, deciding sense amplifiers (SA) activation time is another issue to consider. In this paper, to address the uncertainties of SA activation timing, we propose the bit-line (BL) boosting circuit that supports timing-aware BL sensing. The proposed BL boosting circuit also speed up the BL develop time. The BL boosting circuits have been implemented using 28nm CMOS process, and with 1000 Monte-Carlo simulation, the mean and standard deviation of read delay are reduced by 53.0% and 50.2%, respectively.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5-6
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031591
Publication status	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 2022 Oct 19 → 2022 Oct 22

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	22/10/19 → 22/10/22

Bibliographical note

Funding Information:
The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

Funding Information:
This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591).

Publisher Copyright:
© 2022 IEEE.

Keywords

Low supply voltage
Read delay
SRAM

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISOCC56007.2022.10031591

Cite this

Lee, H., Kim, J., & Park, J. (2022). SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. In Proceedings - International SoC Design Conference 2022, ISOCC 2022 (pp. 5-6). (Proceedings - International SoC Design Conference 2022, ISOCC 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC56007.2022.10031591

SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. / Lee, Hyeyeong; Kim, Joonhyung; Park, Jongsun.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 5-6 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, H, Kim, J & Park, J 2022, SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 5-6, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 22/10/19. https://doi.org/10.1109/ISOCC56007.2022.10031591

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abstract = "Since power consumption reduction has been of particular interest, lowering supply voltage has been widely adopted in system on a chip (SoC) design. In static random access memory (SRAM), read operation with low supply voltage suffers from large read delay to develop the bit-line (BL) voltages using reduced bitcell current. In addition, since process-voltage - temperature (PVT) variations in bitcell current deteriorates at low supply voltage, deciding sense amplifiers (SA) activation time is another issue to consider. In this paper, to address the uncertainties of SA activation timing, we propose the bit-line (BL) boosting circuit that supports timing-aware BL sensing. The proposed BL boosting circuit also speed up the BL develop time. The BL boosting circuits have been implemented using 28nm CMOS process, and with 1000 Monte-Carlo simulation, the mean and standard deviation of read delay are reduced by 53.0% and 50.2%, respectively.",

keywords = "Low supply voltage, Read delay, SRAM",

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note = "Funding Information: The EDA tool was supported by the IC Design Education Center (IDEC), Korea. Funding Information: This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591). Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

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N2 - Since power consumption reduction has been of particular interest, lowering supply voltage has been widely adopted in system on a chip (SoC) design. In static random access memory (SRAM), read operation with low supply voltage suffers from large read delay to develop the bit-line (BL) voltages using reduced bitcell current. In addition, since process-voltage - temperature (PVT) variations in bitcell current deteriorates at low supply voltage, deciding sense amplifiers (SA) activation time is another issue to consider. In this paper, to address the uncertainties of SA activation timing, we propose the bit-line (BL) boosting circuit that supports timing-aware BL sensing. The proposed BL boosting circuit also speed up the BL develop time. The BL boosting circuits have been implemented using 28nm CMOS process, and with 1000 Monte-Carlo simulation, the mean and standard deviation of read delay are reduced by 53.0% and 50.2%, respectively.

AB - Since power consumption reduction has been of particular interest, lowering supply voltage has been widely adopted in system on a chip (SoC) design. In static random access memory (SRAM), read operation with low supply voltage suffers from large read delay to develop the bit-line (BL) voltages using reduced bitcell current. In addition, since process-voltage - temperature (PVT) variations in bitcell current deteriorates at low supply voltage, deciding sense amplifiers (SA) activation time is another issue to consider. In this paper, to address the uncertainties of SA activation timing, we propose the bit-line (BL) boosting circuit that supports timing-aware BL sensing. The proposed BL boosting circuit also speed up the BL develop time. The BL boosting circuits have been implemented using 28nm CMOS process, and with 1000 Monte-Carlo simulation, the mean and standard deviation of read delay are reduced by 53.0% and 50.2%, respectively.

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SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

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