This paper presents a state-parallel MAP (maximum a posteriori) architecture for the turbo decoder of the 3GPP (Generation Partnership Project). Implementation issues are reviewed. Due to the decoding delay and the memory size, the full frame is divided into many sub-frames to apply the decoding algorithm, and the optimal length of a sub-frame is investigated. For higher decoding speeds, the 2's complement modulo scheme is used in normalizing the state metrics, and the best bit-width of the state metric for the modulo scheme is searched. Implementation schemes like the BME (branch metric evaluator) and the state metric evaluator are also presented. Adders of 4-type and several dynamic flip-flops are investigated from the view of power consumption and speed limit. An important aspect of the proposed MAP architecture is its simplicity of control. Hence, the architecture can be easily redesigned according to the size of the sub-frame. The chip's measured power dissipation is 45 mW at a supply voltage of 2.5 V and a clock speed of 50 MHz, and it consists of 100,000 transistors, occupying 1.8 × 1.8 mm2 in 0.25-/μm CMOS technology.
|Number of pages
|Journal of the Korean Physical Society
|Published - 2002 Apr
- Turbo Code
ASJC Scopus subject areas
- General Physics and Astronomy