@inproceedings{7d3a01184a5843f684e342a421fcffa1,
title = "Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device",
abstract = "Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and exposing sequence of two masks to avoid the electrical degradation.",
keywords = "DRAM, Double patterning, Electrical performance, Hotspot, Process specification",
author = "Pyo, {Yu Jin} and Choi, {Soo Han} and Park, {Chul Hong} and Lee, {Sang Hoon} and Yoo, {Moon Hyun} and Kim, {Gyu Tae}",
year = "2011",
doi = "10.1117/12.869978",
language = "English",
isbn = "9780819485335",
series = "Proceedings of SPIE - The International Society for Optical Engineering",
booktitle = "Design for Manufacturability through Design-Process Integration V",
note = "Design for Manufacturability through Design-Process Integration V ; Conference date: 02-03-2011 Through 03-03-2011",
}