Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM
- Jaehyuk Lim
- , Seokchan Yoon
- , Juho Sung
- , Sanghyun Kang
- , Gwon Kim
- , Hyoung Won Baac
- , Changhwan Shin*
*Corresponding author for this work
Research output: Contribution to journal › Article › peer-review
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