Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors: Effect of interface trap charge

B. H. Hong, N. Cho, S. J. Lee, Y. S. Yu, L. Choi, Y. C. Jung, K. H. Cho, K. H. Yeo, D. W. Kim, G. Y. Jin, K. S. Oh, D. Park, S. H. Song, J. S. Rieh, S. W. Hwang

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)

Abstract

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Original languageEnglish
Article number5944946
Pages (from-to)1179-1181
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number9
DOIs
Publication statusPublished - 2011 Sept

Bibliographical note

Funding Information:
Manuscript received April 14, 2010; revised May 22, 2011; accepted June 4, 2011. Date of publication July 12, 2011; date of current version August 24, 2011. This work was supported by the National Research Foundation of Korea grant funded by the Korea government (MEST) under Grant 2011-0000427. The work of S. W. Hwang was supported by Korea University. The review of this letter was arranged by Editor J. Cai.

Keywords

  • Gate-all-around (GAA)
  • interface trap charge
  • silicon nanowire field-effect transistor (SNWFET)
  • subthreshold degradation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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