Swallow counterless DMP PLL

Taewoo Kim; Soonseob Lee; Gwangseog Choi; Soowon Kim; Taegeun Kim

doi:10.1109/ICVC.1999.821013

Swallow counterless DMP PLL

Taewoo Kim, Soonseob Lee, Gwangseog Choi, Soowon Kim, Taegeun Kim

* Honorary professors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a new simple architecture of digital dividing system in dual-modulus prescaler phase-locked loop for wireless communications. In this new architecture a swallow counter is not employed while the same total division ratio as in a conventional system can be obtained. This simple architecture shows advantages in reducing power consumption and gate-counts and is suitable for small die area and low power applications. The circuit is designed in a standard 0.35 um CMOS process.

Original language	English
Title of host publication	ICVC 1999 - 6th International Conference on VLSI and CAD
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	606-608
Number of pages	3
ISBN (Print)	0780357272, 9780780357273
DOIs	https://doi.org/10.1109/ICVC.1999.821013
Publication status	Published - 1999
Event	6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of Duration: 1999 Oct 26 → 1999 Oct 27

Publication series

Name	ICVC 1999 - 6th International Conference on VLSI and CAD

Other

Other	6th International Conference on VLSI and CAD, ICVC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	99/10/26 → 99/10/27

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ICVC.1999.821013

Cite this

Kim, T, Lee, S, Choi, G, Kim, S & Kim, T 1999, Swallow counterless DMP PLL. in ICVC 1999 - 6th International Conference on VLSI and CAD., 821013, ICVC 1999 - 6th International Conference on VLSI and CAD, Institute of Electrical and Electronics Engineers Inc., pp. 606-608, 6th International Conference on VLSI and CAD, ICVC 1999, Seoul, Korea, Republic of, 99/10/26. https://doi.org/10.1109/ICVC.1999.821013

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author = "Taewoo Kim and Soonseob Lee and Gwangseog Choi and Soowon Kim and Taegeun Kim",

year = "1999",

doi = "10.1109/ICVC.1999.821013",

language = "English",

isbn = "0780357272",

series = "ICVC 1999 - 6th International Conference on VLSI and CAD",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Y1 - 1999

N2 - This paper proposes a new simple architecture of digital dividing system in dual-modulus prescaler phase-locked loop for wireless communications. In this new architecture a swallow counter is not employed while the same total division ratio as in a conventional system can be obtained. This simple architecture shows advantages in reducing power consumption and gate-counts and is suitable for small die area and low power applications. The circuit is designed in a standard 0.35 um CMOS process.

AB - This paper proposes a new simple architecture of digital dividing system in dual-modulus prescaler phase-locked loop for wireless communications. In this new architecture a swallow counter is not employed while the same total division ratio as in a conventional system can be obtained. This simple architecture shows advantages in reducing power consumption and gate-counts and is suitable for small die area and low power applications. The circuit is designed in a standard 0.35 um CMOS process.

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M3 - Conference contribution

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SN - 9780780357273

T3 - ICVC 1999 - 6th International Conference on VLSI and CAD

SP - 606

EP - 608

BT - ICVC 1999 - 6th International Conference on VLSI and CAD

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th International Conference on VLSI and CAD, ICVC 1999

Y2 - 26 October 1999 through 27 October 1999

ER -

Swallow counterless DMP PLL

Abstract

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