Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors

Byeong Hyeon Lee; Jae Min Byun; Sangsig Kim; Sang Yeol Lee

doi:10.23919/AM-FPD.2018.8437413

Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors

Byeong Hyeon Lee, Jae Min Byun, Sangsig Kim, Sang Yeol Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.

Original language	English
Title of host publication	AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices
Subtitle of host publication	TFT Technologies and FPD Materials, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9784990875350
DOIs	https://doi.org/10.23919/AM-FPD.2018.8437413
Publication status	Published - 2018 Aug 15
Event	25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018 - Kyoto, Japan Duration: 2018 Jul 3 → 2018 Jul 6

Publication series

Name	AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings

Other

Other	25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018
Country/Territory	Japan
City	Kyoto
Period	18/7/3 → 18/7/6

Bibliographical note

Publisher Copyright:
© 2018 FTFMD.

ASJC Scopus subject areas

Media Technology
Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics

Access to Document

10.23919/AM-FPD.2018.8437413

Cite this

Lee, B. H., Byun, J. M., Kim, S., & Lee, S. Y. (2018). Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. In AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings Article 8437413 (AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/AM-FPD.2018.8437413

Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. / Lee, Byeong Hyeon; Byun, Jae Min; Kim, Sangsig et al.
AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8437413 (AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, BH, Byun, JM, Kim, S & Lee, SY 2018, Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. in AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings., 8437413, AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings, Institute of Electrical and Electronics Engineers Inc., 25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018, Kyoto, Japan, 18/7/3. https://doi.org/10.23919/AM-FPD.2018.8437413

Lee BH, Byun JM, Kim S, Lee SY. Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. In AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8437413. (AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings). doi: 10.23919/AM-FPD.2018.8437413

Lee, Byeong Hyeon ; Byun, Jae Min ; Kim, Sangsig et al. / Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. (AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings).

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abstract = "Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.",

author = "Lee, {Byeong Hyeon} and Byun, {Jae Min} and Sangsig Kim and Lee, {Sang Yeol}",

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AU - Kim, Sangsig

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Y1 - 2018/8/15

N2 - Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.

AB - Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.

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Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors

Abstract

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Bibliographical note

ASJC Scopus subject areas

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