Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure

Changho Shin, Jeong Kyu Kim, Changhwan Shin, Jong Kook Kim, Hyun Yong Yu

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage (Vth) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced Vth in a FinFET with an S/D doping concentration (NS/D) of 5 × 1020 cm-3 is 9.277 mV. In order to suppress RDF-induced Vth variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an NS/D = 5 × 1019 cm-3) results in a standard deviation of 4.729 mV for RDF-induced Vth, while maintaining the on-state drive current (Ion) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to Vth variation with the adoption of the proposed M-I-S S/D structure.

Original languageEnglish
Pages (from-to)618-622
Number of pages5
JournalCurrent Applied Physics
Issue number6
Publication statusPublished - 2016 Jun

Bibliographical note

Funding Information:
This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea within the Ministry of Science, ICT, and Future Planning under Grant 2014R1A1A1036090 and in part by the Technology Innovation Program through the Ministry of Trade, Industry and Energy, Korea , under Grant 10052804 .

Publisher Copyright:
© 2016 Elsevier B.V. All rights reserved.


  • CMOS
  • FinFET
  • Metal-interlayer-semiconductor
  • Random dopant fluctuation
  • Variation

ASJC Scopus subject areas

  • General Materials Science
  • General Physics and Astronomy


Dive into the research topics of 'Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure'. Together they form a unique fingerprint.

Cite this