Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices

Chankeun Yoon; Changhwan Shin

doi:10.1016/j.sse.2019.107698

Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices

Chankeun Yoon
, Changhwan Shin^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

The performance of fully depleted silicon on insulator (FDSOI) device and ferroelectric-gated FDSOI (FE-FDSOI) device are investigated for various gate voltage sweep rates. Regardless of the gate voltage sweep rates, the input transfer characteristics of the baseline FDOSI device are not varied. On the contrary, it was observed that the hysteresis width of the FE-FDSOI device is affected by the gate voltage sweep rates. As the gate voltage sweep rate decreases, the ratio of ferroelectric remnant polarization to coercive voltage (P_r/V_c) increases, so that the magnitude of the ferroelectric negative capacitance (|C_FE|) increases. This affects hysteresis condition of the FE-FDSOI device, therefore, the hysteresis width of the FE-FDSOI device decreases as the gate voltage sweep rate decreases. According to the results, it is suggested that voltage sweep rate be decreased to decrease the hysteresis width of FE-FDSOI device.

Original language	English
Article number	107698
Journal	Solid-State Electronics
Volume	164
DOIs	https://doi.org/10.1016/j.sse.2019.107698
Publication status	Published - 2020 Feb
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2019 Elsevier Ltd

Keywords

Fully-depleted silicon-on-insulator
Hysteresis
Negative capacitance
Steep switching

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1016/j.sse.2019.107698

Cite this

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title = "Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices",

abstract = "The performance of fully depleted silicon on insulator (FDSOI) device and ferroelectric-gated FDSOI (FE-FDSOI) device are investigated for various gate voltage sweep rates. Regardless of the gate voltage sweep rates, the input transfer characteristics of the baseline FDOSI device are not varied. On the contrary, it was observed that the hysteresis width of the FE-FDSOI device is affected by the gate voltage sweep rates. As the gate voltage sweep rate decreases, the ratio of ferroelectric remnant polarization to coercive voltage (Pr/Vc) increases, so that the magnitude of the ferroelectric negative capacitance (|CFE|) increases. This affects hysteresis condition of the FE-FDSOI device, therefore, the hysteresis width of the FE-FDSOI device decreases as the gate voltage sweep rate decreases. According to the results, it is suggested that voltage sweep rate be decreased to decrease the hysteresis width of FE-FDSOI device.",

keywords = "Fully-depleted silicon-on-insulator, Hysteresis, Negative capacitance, Steep switching",

author = "Chankeun Yoon and Changhwan Shin",

note = "Publisher Copyright: {\textcopyright} 2019 Elsevier Ltd",

year = "2020",

month = feb,

doi = "10.1016/j.sse.2019.107698",

language = "English",

volume = "164",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Ltd",

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TY - JOUR

T1 - Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices

AU - Yoon, Chankeun

AU - Shin, Changhwan

PY - 2020/2

Y1 - 2020/2

N2 - The performance of fully depleted silicon on insulator (FDSOI) device and ferroelectric-gated FDSOI (FE-FDSOI) device are investigated for various gate voltage sweep rates. Regardless of the gate voltage sweep rates, the input transfer characteristics of the baseline FDOSI device are not varied. On the contrary, it was observed that the hysteresis width of the FE-FDSOI device is affected by the gate voltage sweep rates. As the gate voltage sweep rate decreases, the ratio of ferroelectric remnant polarization to coercive voltage (Pr/Vc) increases, so that the magnitude of the ferroelectric negative capacitance (|CFE|) increases. This affects hysteresis condition of the FE-FDSOI device, therefore, the hysteresis width of the FE-FDSOI device decreases as the gate voltage sweep rate decreases. According to the results, it is suggested that voltage sweep rate be decreased to decrease the hysteresis width of FE-FDSOI device.

AB - The performance of fully depleted silicon on insulator (FDSOI) device and ferroelectric-gated FDSOI (FE-FDSOI) device are investigated for various gate voltage sweep rates. Regardless of the gate voltage sweep rates, the input transfer characteristics of the baseline FDOSI device are not varied. On the contrary, it was observed that the hysteresis width of the FE-FDSOI device is affected by the gate voltage sweep rates. As the gate voltage sweep rate decreases, the ratio of ferroelectric remnant polarization to coercive voltage (Pr/Vc) increases, so that the magnitude of the ferroelectric negative capacitance (|CFE|) increases. This affects hysteresis condition of the FE-FDSOI device, therefore, the hysteresis width of the FE-FDSOI device decreases as the gate voltage sweep rate decreases. According to the results, it is suggested that voltage sweep rate be decreased to decrease the hysteresis width of FE-FDSOI device.

KW - Fully-depleted silicon-on-insulator

KW - Hysteresis

KW - Negative capacitance

KW - Steep switching

UR - https://www.scopus.com/pages/publications/85076012815

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DO - 10.1016/j.sse.2019.107698

M3 - Article

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SN - 0038-1101

VL - 164

JO - Solid-State Electronics

JF - Solid-State Electronics

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ER -

Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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