Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience

Hyeong Kon Bae, Myung Jae Chung, Young Ho Gong, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the continuous scaling of process technology, DRAM reliability has become a critical challenge in modern memory systems. Currently, DRAM memory systems for servers employ ECC DIMMs with a single error correction and double error detection (SECDED) code. However, the SECDED code is insufficient to ensure DRAM reliability since memory systems become more susceptible to errors. Though various studies have proposed multi-bit correctable ECC schemes, such ECC schemes cause performance and/or storage overhead. To minimize performance degradation while providing strong error resilience, in this paper, we propose Twin ECC, a low-cost memory protection scheme through data duplication. In a 512-bit data, Twin ECC duplicates meaningful data into meaningless zeros. Since '1' → '0' error pattern is dominant in DRAM cells, Twin ECC provides strong error resilience by performing bitwise OR operations between the original meaningful data and duplicated data. After the bitwise OR operations, Twin ECC adopts the SECDED code for further enhancing data protection. Our evaluations show that Twin ECC reduces the system failure probability by average 64.8%, 56.9%, and 49.5%, when the portion of '1 ' → '0' error is 100%, 90%, and 80%, respectively, while causing only 0.7% performance overhead and no storage overhead compared to the baseline ECC DIMM with SECDED code.

Original languageEnglish
Title of host publication2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9783981926378
DOIs
Publication statusPublished - 2023
Event2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Antwerp, Belgium
Duration: 2023 Apr 172023 Apr 19

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume2023-April
ISSN (Print)1530-1591

Conference

Conference2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023
Country/TerritoryBelgium
CityAntwerp
Period23/4/1723/4/19

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2020R1A2C2003500), Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2022-0-00441-001, Memory-Centric Architecture Using the Reconfigurable PIM Devices), and Samsung Electronics. We would like to thank Prof. Jung Ho Ahn for providing helpful insights. Sung Woo Chung and Young-Ho Gong are the co-corresponding authors of this paper.

Publisher Copyright:
© 2023 EDAA.

Keywords

  • DRAM reliability
  • bitwise operation
  • data duplication
  • error correction code

ASJC Scopus subject areas

  • General Engineering

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