Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

Namhyung Kim; Kiryong Song; Jongwon Yun; Junghwan Yoo; Jae Sung Rieh

doi:10.1109/TMTT.2016.2581816

Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

Namhyung Kim, Kiryong Song, Jongwon Yun, Junghwan Yoo, Jae Sung Rieh

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 × 760 μm^² (PLL1) and 1300 × 840 μm² (PLL2) including probing pads.

Original language	English
Article number	7506100
Pages (from-to)	2623-2630
Number of pages	8
Journal	IEEE Transactions on Microwave Theory and Techniques
Volume	64
Issue number	8
DOIs	https://doi.org/10.1109/TMTT.2016.2581816
Publication status	Published - 2016 Aug

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIP) (No. 2011-0020128).

Publisher Copyright:
© 2016 IEEE.

Keywords

Phase noise
phase-locked loop (PLL)
voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

Radiation
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/TMTT.2016.2581816

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title = "Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology",

abstract = "Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 × 760 μm^2 (PLL1) and 1300 × 840 μm2 (PLL2) including probing pads.",

keywords = "Phase noise, phase-locked loop (PLL), voltage-controlled oscillator (VCO)",

author = "Namhyung Kim and Kiryong Song and Jongwon Yun and Junghwan Yoo and Rieh, {Jae Sung}",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIP) (No. 2011-0020128). Publisher Copyright: {\textcopyright} 2016 IEEE.",

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doi = "10.1109/TMTT.2016.2581816",

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AU - Yoo, Junghwan

AU - Rieh, Jae Sung

PY - 2016/8

Y1 - 2016/8

N2 - Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 × 760 μm^2 (PLL1) and 1300 × 840 μm2 (PLL2) including probing pads.

AB - Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 × 760 μm^2 (PLL1) and 1300 × 840 μm2 (PLL2) including probing pads.

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Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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