Unbiased Finite-Memory Digital Phase-Locked Loop

Sung Hyun You; Jung Min Pak; Choon Ki Ahn; Peng Shi; Myo Taeg Lim

doi:10.1109/TCSII.2016.2531138

Unbiased Finite-Memory Digital Phase-Locked Loop

Sung Hyun You, Jung Min Pak, Choon Ki Ahn, Peng Shi, Myo Taeg Lim

Research output: Contribution to journal › Article › peer-review

26 Citations (Scopus)

Abstract

Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.

Original language	English
Article number	7410011
Pages (from-to)	798-802
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	63
Issue number	8
DOIs	https://doi.org/10.1109/TCSII.2016.2531138
Publication status	Published - 2016 Aug

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation (NRF) through the Ministry of Science, ICT, and Future Planning under Grant NRF- 2014R1A1A1006101; by the Human Resources Program in Energy Technology through the Korea Institute of Energy Technology Evaluation and Planning within the Ministry of Trade, Industry, and Energy, South Korea, under Grant 20154030200610; by the National Natural Science Foundation of China under Grant 61573112; and by the Australian Research Council under Grant DP140102180, Grant LP140100471, and Grant LE150100079.

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

Digital phase-locked loop (DPLL)
finite-memory structure
unbiasedness

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2016.2531138

Cite this

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title = "Unbiased Finite-Memory Digital Phase-Locked Loop",

abstract = "Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.",

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note = "Funding Information: This work was supported in part by the National Research Foundation (NRF) through the Ministry of Science, ICT, and Future Planning under Grant NRF- 2014R1A1A1006101; by the Human Resources Program in Energy Technology through the Korea Institute of Energy Technology Evaluation and Planning within the Ministry of Trade, Industry, and Energy, South Korea, under Grant 20154030200610; by the National Natural Science Foundation of China under Grant 61573112; and by the Australian Research Council under Grant DP140102180, Grant LP140100471, and Grant LE150100079. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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N1 - Funding Information: This work was supported in part by the National Research Foundation (NRF) through the Ministry of Science, ICT, and Future Planning under Grant NRF- 2014R1A1A1006101; by the Human Resources Program in Energy Technology through the Korea Institute of Energy Technology Evaluation and Planning within the Ministry of Trade, Industry, and Energy, South Korea, under Grant 20154030200610; by the National Natural Science Foundation of China under Grant 61573112; and by the Australian Research Council under Grant DP140102180, Grant LP140100471, and Grant LE150100079. Publisher Copyright: © 2004-2012 IEEE.

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N2 - Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.

AB - Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.

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Unbiased Finite-Memory Digital Phase-Locked Loop

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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