Variability-insensitive scheme for NAND flash memory interfaces

C. I. Son; S. Yoon; S. W. Chung; C. I. Park; E. Y. Chung

doi:10.1049/el:20062239

Variability-insensitive scheme for NAND flash memory interfaces

C. I. Son, S. Yoon, S. W. Chung, C. I. Park, E. Y. Chung

Research output: Contribution to journal › Article › peer-review

Abstract

A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

Original language	English
Pages (from-to)	1335-1337
Number of pages	3
Journal	Electronics Letters
Volume	42
Issue number	23
DOIs	https://doi.org/10.1049/el:20062239
Publication status	Published - 2006

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:20062239

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AB - A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

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Variability-insensitive scheme for NAND flash memory interfaces

Abstract

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