Variability-insensitive scheme for NAND flash memory interfaces

C. I. Son; S. Yoon; S. W. Chung; C. I. Park; E. Y. Chung

doi:10.1049/el:20062239

Variability-insensitive scheme for NAND flash memory interfaces

C. I. Son, S. Yoon, S. W. Chung, C. I. Park, E. Y. Chung

Department of Computer Science and Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

Original language	English
Pages (from-to)	1335-1337
Number of pages	3
Journal	Electronics Letters
Volume	42
Issue number	23
DOIs	https://doi.org/10.1049/el:20062239
Publication status	Published - 2006

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:20062239

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@article{49d01d6ca0e24a538fc0cf2c80ede631,

title = "Variability-insensitive scheme for NAND flash memory interfaces",

abstract = "A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.",

author = "Son, {C. I.} and S. Yoon and Chung, {S. W.} and Park, {C. I.} and Chung, {E. Y.}",

year = "2006",

doi = "10.1049/el:20062239",

language = "English",

volume = "42",

pages = "1335--1337",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "23",

}

TY - JOUR

T1 - Variability-insensitive scheme for NAND flash memory interfaces

AU - Son, C. I.

AU - Yoon, S.

AU - Chung, S. W.

AU - Park, C. I.

AU - Chung, E. Y.

PY - 2006

Y1 - 2006

N2 - A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

AB - A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

UR - http://www.scopus.com/inward/record.url?scp=33750925526&partnerID=8YFLogxK

U2 - 10.1049/el:20062239

DO - 10.1049/el:20062239

M3 - Article

AN - SCOPUS:33750925526

SN - 0013-5194

VL - 42

SP - 1335

EP - 1337

JO - Electronics Letters

JF - Electronics Letters

IS - 23

ER -

Variability-insensitive scheme for NAND flash memory interfaces

Abstract

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