Variation-aware low-power video processor design techniques

With recent advances in scaled CMOS process technology, CMOS VLSI systems suffers from severe process-voltage-temperature (PVT) variations. Aggressive supply voltage scaling is also accompanied with technology scaling, which even aggravates the worst-case speed variations and noise margin of embedded SRAM memories. This paper presents variation-tolerant design techniques for video coding and decoding (CODEC) processor, which is mainly composed of computational data-path and embedded SRAM memories. First, we present an adaptive clock generation method to remove the delay failures in data-path operating with sub or near-threshold supply voltage. The variation-aware clock generation scheme can monitor the timing-variations and efficiently control the clock cycles to minimize the delay failures causes by timing variations. In low voltage operations, embedded SRAM memories also suffer from many functional failures. Priority based embedded memory design approaches, which are selective error correction coding (ECC) and variable sizing scheme for SRAM, are also presented to mitigate the video quality loss with serious functional failures in embedded memory.