Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al2O3/Si3N4/SiO2/poly-Si capacitors

Suk Bum Hong; Ju Hyun Park; Tae Ho Lee; Jun Hee Lim; Changhwan Shin; Young Woo Park; Tae Geun Kim

doi:10.1016/j.apsusc.2017.11.226

Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si capacitors

Suk Bum Hong
, Ju Hyun Park
, Tae Ho Lee
, Jun Hee Lim
, Changhwan Shin
, Young Woo Park
, Tae Geun Kim^*

^*Corresponding author for this work

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

This study presents the improved memory properties of TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H₂ and D₂ molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO₂ interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.

Original language	English
Pages (from-to)	104-110
Number of pages	7
Journal	Applied Surface Science
Volume	477
DOIs	https://doi.org/10.1016/j.apsusc.2017.11.226
Publication status	Published - 2019 May 31

Bibliographical note

Publisher Copyright:
© 2017 Elsevier B.V.

Keywords

Grain boundary
Interface trap
Poly-silicon channel
Rapid thermal annealing
TANOS

ASJC Scopus subject areas

Condensed Matter Physics
Surfaces and Interfaces
Surfaces, Coatings and Films

Access to Document

10.1016/j.apsusc.2017.11.226

Cite this

@article{093ed48bf8eb4e3fb097f5ef936686e2,

title = "Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al2O3/Si3N4/SiO2/poly-Si capacitors",

abstract = "This study presents the improved memory properties of TiN/Al2O3/Si3N4/SiO2/poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H2 and D2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.",

keywords = "Grain boundary, Interface trap, Poly-silicon channel, Rapid thermal annealing, TANOS",

author = "Hong, \{Suk Bum\} and Park, \{Ju Hyun\} and Lee, \{Tae Ho\} and Lim, \{Jun Hee\} and Changhwan Shin and Park, \{Young Woo\} and Kim, \{Tae Geun\}",

note = "Publisher Copyright: {\textcopyright} 2017 Elsevier B.V.",

year = "2019",

month = may,

day = "31",

doi = "10.1016/j.apsusc.2017.11.226",

language = "English",

volume = "477",

pages = "104--110",

journal = "Applied Surface Science",

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publisher = "Elsevier B.V.",

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TY - JOUR

T1 - Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al2O3/Si3N4/SiO2/poly-Si capacitors

AU - Hong, Suk Bum

AU - Park, Ju Hyun

AU - Lee, Tae Ho

AU - Lim, Jun Hee

AU - Shin, Changhwan

AU - Park, Young Woo

AU - Kim, Tae Geun

PY - 2019/5/31

Y1 - 2019/5/31

N2 - This study presents the improved memory properties of TiN/Al2O3/Si3N4/SiO2/poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H2 and D2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.

AB - This study presents the improved memory properties of TiN/Al2O3/Si3N4/SiO2/poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H2 and D2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.

KW - Grain boundary

KW - Interface trap

KW - Poly-silicon channel

KW - Rapid thermal annealing

KW - TANOS

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U2 - 10.1016/j.apsusc.2017.11.226

DO - 10.1016/j.apsusc.2017.11.226

M3 - Article

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EP - 110

JO - Applied Surface Science

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