VLSI architecture for fast motion estimation based on bit-plane matching

In this paper, we propose a VLSI (very large scale integrated circuit) architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation by using a 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using only simple Boolean functions, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By controlling the data flow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and can exploit lower-cost fabrication technology. The proposed system was designed to process reference blocks of size 16 × 16 and the search range of [-16, 15]. We modeled and tested the proposed motion estimator in VHDL (very high speed integrated circuit hardware description language) and then synthesized the whole system which has been integrated in a 0.6-μm triple-metal CMOS chip of size 8.15 × 10.84 mm².