Wide frequency range duty cycle correction circuit for DDR interface

Dongsuk Shin; Soo Won Kim; Chulwoo Kim

doi:10.1587/elex.5.254

Wide frequency range duty cycle correction circuit for DDR interface

Dongsuk Shin^*
, Soo Won Kim
, Chulwoo Kim

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2 GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18 μm CMOS technology.

Original language	English
Pages (from-to)	254-259
Number of pages	6
Journal	ieice electronics express
Volume	5
Issue number	8
DOIs	https://doi.org/10.1587/elex.5.254
Publication status	Published - 2008 Apr 25

Keywords

Double date rate
Duty cycle correction
Duty detector

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1587/elex.5.254

Cite this

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abstract = "The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50\% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2 GHz with ±10\% duty ratio error, the output duty ratio error is corrected to be less than ±1.4\%. The proposed DCC circuit is designed and verified using a 0.18 μm CMOS technology.",

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AU - Shin, Dongsuk

AU - Kim, Soo Won

AU - Kim, Chulwoo

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N2 - The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2 GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18 μm CMOS technology.

AB - The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2 GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18 μm CMOS technology.

KW - Double date rate

KW - Duty cycle correction

KW - Duty detector

UR - https://www.scopus.com/pages/publications/45249106193

U2 - 10.1587/elex.5.254

DO - 10.1587/elex.5.254

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ER -

Wide frequency range duty cycle correction circuit for DDR interface

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

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