TY - JOUR
T1 - Wired-OR property and improved structure of recovered energy logic (REL)
AU - Kim, Chulwoo
AU - Kim, Soowon
PY - 1997
Y1 - 1997
N2 - A modified MOS REL structure, which explores the wired-OR property and enhances speed and power characteristics, is proposed. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay of the MOS REL inverter is enhanced by 26% with less silicon area. Recovered energy logic, \Virctl-OR property, Adiabatic logic, Inverters
AB - A modified MOS REL structure, which explores the wired-OR property and enhances speed and power characteristics, is proposed. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay of the MOS REL inverter is enhanced by 26% with less silicon area. Recovered energy logic, \Virctl-OR property, Adiabatic logic, Inverters
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U2 - 10.1049/ip-cds:19971288
DO - 10.1049/ip-cds:19971288
M3 - Article
AN - SCOPUS:0031356301
SN - 1350-2409
VL - 144
SP - 378
EP - 380
JO - IEE Proceedings: Circuits, Devices and Systems
JF - IEE Proceedings: Circuits, Devices and Systems
IS - 6
ER -