Wired-OR property and improved structure of recovered energy logic (REL)

Chulwoo Kim; Soo-Won Kim

doi:10.1049/el:19970500

Wired-OR property and improved structure of recovered energy logic (REL)

Chulwoo Kim
, Soo-Won Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A modified MOS REL structure is proposed, which exhibits the wired-OR property and enhances speed and power characteristics. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay product of an MOS REL inverter is enhanced by 26% with a smaller silicon area.

Original language	English
Pages (from-to)	760-762
Number of pages	3
Journal	Electronics Letters
Volume	33
Issue number	9
DOIs	https://doi.org/10.1049/el:19970500
Publication status	Published - 1997 Apr 24

Keywords

Logic circuits
Logic design

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19970500

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title = "Wired-OR property and improved structure of recovered energy logic (REL)",

abstract = "A modified MOS REL structure is proposed, which exhibits the wired-OR property and enhances speed and power characteristics. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay product of an MOS REL inverter is enhanced by 26\% with a smaller silicon area.",

keywords = "Logic circuits, Logic design",

author = "Chulwoo Kim and Soo-Won Kim",

year = "1997",

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doi = "10.1049/el:19970500",

language = "English",

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journal = "Electronics Letters",

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N2 - A modified MOS REL structure is proposed, which exhibits the wired-OR property and enhances speed and power characteristics. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay product of an MOS REL inverter is enhanced by 26% with a smaller silicon area.

AB - A modified MOS REL structure is proposed, which exhibits the wired-OR property and enhances speed and power characteristics. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay product of an MOS REL inverter is enhanced by 26% with a smaller silicon area.

KW - Logic circuits

KW - Logic design

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UR - https://www.scopus.com/pages/publications/5244335944#tab=citedBy

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JO - Electronics Letters

JF - Electronics Letters

IS - 9

ER -

Wired-OR property and improved structure of recovered energy logic (REL)

Abstract

Keywords

ASJC Scopus subject areas

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