Worst case sampling method to estimate the impact of random variation on static random access memory

We propose a worst case sampling method for quantitatively estimating the impact of random variation on static random access memory (SRAM) cells. This method enables us to predict the values of SRAM read/write metrics beyond the Six Sigma regime. First, we developed a compact model with a Monte Carlo simulation. The model includes both device modeling and sample size extension to predict and quickly estimate SRAM read/write metrics accurately. We verified the accuracy of the model by comparing the simulation results to previously published silicon data. Our results provide circuit designers with insight into the impact of random variations on SRAM cells. In particular, we demonstrate how SRAM cell operations can be protected from harsh random variations using word-line voltage margins as the key parameter.